As dynamic random access memory (DRAM) device dimensions continue to shrink, the need to achieve a high stored charge for a given cell area becomes increasingly important. In the past, several approaches have been proposed to obtain a high stored charge per unit area by increasing the effective capacitor plate (usually made of polysilicon) surface by roughening or texturizing the polysilicon surface.
One process example for texturizing polycrystalline silicon (hereinafter also "polysilicon" or "poly") is discussed in an article entitled "Rugged Surface Poly-Si Electrode and Low Temperature Deposited Si3N4 for 64 Mb and Beyond STC DRAM Cell" authored by M. Yoshimaru et al., Oki Electric Industry Co., Ltd., VLSI R&D Laboratory 550-1, Higashiasakawa, Hachioji, Tokyo 193, Japan. In this article, using a poly deposition temperature of 570 degrees Celsius causes the poly layer surface to become rugged (or textured). The article claims (in the third paragraph of the first page) that applying this technique to form a stacked storage node cell plate in a DRAM, results in an increase of the cell plate's surface area of up to 2.5 times that of a standard stacked capacitor cell (STC).
However, main drawbacks with this method are that the temperature must be precisely controlled (within +/-3 degrees C. of 570.degree. C.) during deposition to form the rugged poly surface and subjecting the rugged poly to temperatures above 570 degrees C. in subsequent process steps will cause the rugged surface to flatten out. As is the case with many polysilicon texturizing techniques, the method discussed above requires tight process control tolerances and process complexity that may prevent current polysilicon texturizing techniques to be incorporated into production. Also, the amount of increase in capacitance obtained may not be sufficient for certain cell designs.
In the present invention, a stable and uniform texturized surface on a storage node capacitor cell plate is developed by less complex process steps and the cell plate will retain its textured surface throughout implementation of conventional DRAM fabrication processes.